Interconnection for computer communication applications such as clock distribution, memory and interprocessor data bus, matrix or cross-point switches are key elements in system architecture, package design, function, and performance. Arrays of transmission-lines into fluid-sealed semiconductor chip packages further pose problems in strain-relief at device interfaces, fan-out distribution, integrability, and spatial efficiency. Some of these known problems have been resolved by this invention.
Dense pin-in-hole electrical connectors for today's multichip module (MCM) packaging generates electromagnetic inductance and coupled noise. Furthermore, as the electrical signal passes from the I/O pin to the surface of the MLC substrate, the Delta-i noise induced within multilayer ceramic substrates by semiconductor chips, simultaneously switching logic levels further degrades the electrical signals. In general, these problems of noise and dispersion increase directly with increasing signal frequency, particularly above 100 megahertz.
The distribution of a master oscillator or a system clock to the multichip array on the substrate requires controlled, adjusted time-delay offsets to guarantee simultaneous clock signal arrivals. Departures from simultaneity are known as "skew," and, translate directly into computer cycle-time performance.
This invention addresses these concerns and provides means for resolving some of the issues. For example, it was found that direct connection to the substrate interface minimizes connector and substrate noise. Therefore, the preferred connection for high frequency operation is a cable-TCM interface, where the connection penetrates the side of the TCM (Thermal Conduction Module) and where a receiver is provided at the substrate surface. Strain-relief of the relatively rigid coaxial cable and provision for fluid sealing of the cable-module interface are also addressed in this invention.
The requirement to compensate for clock arrival time differences related to propagation times for nets of different lengths has also been addressed by this invention. The designed delays that are deliberately introduced between ICE's (Interface Control Element), SCE's (System Control Element), etc. within and between printed circuit (PC) boards of thermal conduction modules (TCM) are similarly accommodated by this invention.
Some of the important features of this invention are:
(1) the transmission-line to the module interface, PA1 (2) transmission-line substrate interface, PA1 (3) variable delay-line embodiments, PA1 (4) transmission-line guide, support, fluid seal and strain-relief means, and PA1 (5) separability of the upper and lower module half-planes for repair, test, or engineering change. PA1 a) penetrating the controlled environment of the TCM (Thermal Conduction Module) with one or more coaxial cables; PA1 b) aligning and securing the coaxial cable through a guide groove; PA1 c) locating and aligning the coaxial cable ends to receiver, driver, or both; PA1 d) mounting of receiver and/or driver devices on the substrate of the TCM; PA1 e) effecting a separable interface between the coaxial cable and the receiver or driver circuits, and PA1 f) providing integral variable time-delay means. PA1 a) a substrate, PA1 b) at least one electrical contact pair in contact with at least one surface of the substrate, PA1 c) at least a portion of at least one transmission-line electrically communicating with the at least one electrical contact pair, PA1 d) a housing protecting the at least one electrical contact pair and the substrate, and, PA1 e) means in the housing for communicating an electrical signal through the housing to the electrical contact pair from the at least one transmission-line. PA1 a) a substrate, PA1 b) at least one electrical contact pair in contact with at least one surface of the substrate, PA1 c) at least one electrical transmission-line, PA1 d) means for guiding the at least one electrical transmission-line to the at least one electrical contact pair, PA1 e) means for aligning and securing the at least one electrical transmission-line to the at least one electrical contact pair, PA1 f) a housing protecting the at least one electrical contact pair and the substrate, and PA1 g) means in the housing for communicating an electrical signal through the housing to the at least one electrical contact pair from the at least one electrical transmission-line. PA1 a) securing at least one electrical contact pair in contact with at least one surface of a substrate, PA1 b) securing at least one electrical transmission-line to the at least one electrical contact pair, PA1 c) providing a housing to protect the at least one electrical contact pair and the substrate, and PA1 d) providing means in the housing for communicating an electrical signal through the housing to the electrical contact pair from the at least one transmission-line. PA1 a) securing at least one electrical contact pair in contact with at least one surface of a substrate, PA1 b) providing means for guiding at least one electrical transmission-line to the electrical contact pair, PA1 c) providing means for aligning and securing the at least one electrical transmission-line to the at least one electrical contact pair, PA1 d) providing a housing to protect the at least one electrical contact pair and the substrate, and PA1 e) providing means in the housing for communicating an electrical signal through the housing to the at least one electrical pair from the at least one electrical transmission-line.
Problems in strain-relief at device interfaces, fan-out distribution, integrability, and spatial efficiency are some of the other problems that one has to contend with. Some of these known problems have been resolved by this invention.
The present invention teaches compatible designs for interfacing external transmission-lines into a fluid-sealed, temperature-controlled module, and, direct distribution within the module to selectable semiconductor chip positions. The present invention further teaches direct surface connection of the transmission-line to the substrate surface, and thus avoids the passage of the electrical signal through the module layers or cooling structures.
This invention also allows the presence of C-4s and the semiconductor chips on the substrate while providing unique means for electrical interconnection of the transmission-line to a receiver on the substrate surface. Means for suitably bonding the transmission-line or the signal conductor to a via in the substrate is also provided.
Another, unique feature of this invention are the bellows for the transmission-line which provide, fluid sealing and strain-relief for the connection of the transmission-line at the substrate surface.